1. Field of the Invention
The invention is related to a method of fabricating a dual damascene structure, and more particularly, to a method of fabricating a dual damascene structure integrating all etching steps in the same etching chamber.
2. Description of the Prior Art
The multilevel interconnects of an integrated circuit are fabricated by damascene processes, which include single damascene and dual damascene processes. The dual damascene process may reduce 20-30% of the steps of fabrication and also reduce the contact resist between metal lines and vias to improve reliability. Therefore, most of the metal interconnections in the integrated circuit are formed by dual damascene processes. At present, the conventional method of fabricating a dual damascene structure is to etch low-K dielectric layers to form a trench and a via hole. Then, the via hole and the trench are filled with copper, and a planarization process is performed to form the metal interconnects. This structure may reduce the resist and the parasitic capacity of the metal interconnections, and accelerate signal transduction. The etching process has a very important role in dual damascene processes.
Different forming sequences of dual damascene structure, such as a trench-first dual damascene process, a via-first dual damascene process, and a partial-via-first dual damascene process, use plasma gas to etch the dielectric layers. The etching chamber is kept in a vacuum. Most conventional etching chambers employ a “deposition mode” during wafer processing, i.e. a polymer layer is deposited on the wall surface of the etching chamber before etching. This may prevent the plasma gas from etching the wall surface of the etching chamber, which causes metal contamination. In addition, the polymer layer has a higher selectivity than the photoresist pattern used as a mask during etching. After the first etching process step, such as a via hole etching process, however, the photoresist pattern is removed in an ashing process and a cleaning step. Sequentially, another etching mask or photoresist pattern is formed to perform the second etching process step, such as a trench etching process. Because the majority of the photoresist is organic material, an additional photoresist stripper is used to remove the photoresist pattern. Therefore, the etching chamber has to be vented to remove the semiconductor wafer, and the semiconductor wafer is transferred to the photoresist stripper for the following ashing and cleaning processes. Afterward, the semiconductor wafer is returned to the etching chamber and the chamber is once more placed in a vacuum for performing the next etching process step. If, however, the photoresist is removed directly by an oxygen plasma gas in the etching chamber, the polymer layer on the wall surface of the etching chamber may be removed along with the photoresist.
Different etching processes may be performed in one etching chamber. This can cause a prior etching process to affect a later one. This is known as a “memory effect”. The unstable environment of the etching chamber causes the dual damascene structure to be of poor quality and affects the stability of the semiconductor device. For this reason, the etching process and the ashing process of the dual damascene structure have to be performed in different etching chambers, or even in different machines. The prior art method of forming the dual damascene structure includes steps of: 1) venting the etching chamber; 2) transferring the semiconductor wafer between different machines; 3) vacuuming the etching chamber; and 4) transferring the semiconductor wafer by mechanical arms. In addition, the time required for forming the dual damascene structure also includes the time for warming machines. Complex steps of the transportation process may also affect the yield of the fabrication.